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data bulletin MX839 ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. digitally controlled analog i/o processor preliminary information features applications x 4 input intelligent 10 bit a/d monitoring subsystem 4 high and 4 low comparators external irq generator free running operation x three 8/10 bit dacs x two variable attenuators x selectable a/d clock frequencies x full control via 4-wire serial interface x low power 3.0 operation x pcs, cellular, lmr, wireless transceivers, and general purpose x monitor and control: rssi, battery state, temperature, vswr, and error voltages x digital trim and calibration: vcos, tcxo, power output, bias, current, if gain, deviation, modulation depth, and baseband gain rssi vswr tx power ref. offset trim mod 1 out m c battery state temperature receiver rf transmitter transmitter modulator radio battery system MX839 4 x 10 bit free run a/d 4 x hi comparator 4 x low comparator irq on compare 2 x variable attenuator 3 x 8/10 bit dac clock osc & dividers c-bus interface & control logic vco trim mod 1 in c-bus serial bus 0 : 3 mod 2 out mod 2 in the MX839 is a low power cmos c peripheral device which provides digitally controlled calibration, trimming, and monitoring functions for pcs, cellular, lmr, wireless transceivers, and general purpose applications. featuring a four input intelligent 10 bit a/d monitoring subsystem, an interrupt generator, three 8/10 bit dacs, and two variable attenuator functions, the MX839 automatically monitors, produces, and trims up to nine analog signals via a simple four wire serial control bus. the free running a/d intelligent monitoring subsystem includes independent high and low limit comparators for each of four analog input signals which can be configured to generate external c interrupts. the MX839s high level of integration reduces end product parts count, component size, and software complexity. MX839 digital trimming functions also reduce manufacturing costs by eliminating manual trimming operations. featuring an operating range of 3.0v to 5.5v the MX839 is available in 24-pin ssop (MX839ds), 24-pin soic (MX839dw), and 24-pin pdip (MX839p) packages.
digitally controlled analog i/o processor 2 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. contents section page 1 block diagram ................................................................................................................. ............... 3 2 signal list ................................................................................................................... .................... 4 3 external components........................................................................................................... .......... 5 4 general description ........................................................................................................... ............ 6 4.1 variable attenuators........................................................................................................ ....................... 6 4.2 digital to analog converters................................................................................................ ................... 6 4.3 analog to digital converter and a/d clock generator ......................................................................... .. 6 4.4 magnitude comparators and interrupt request ................................................................................. .... 7 4.5 software description ........................................................................................................ ...................... 7 4.6 read only registers (8-bit and 16-bit) ...................................................................................... ............ 9 4.7 write only register description ............................................................................................. ................ 9 4.8 read only register description .............................................................................................. .............. 13 5 application ................................................................................................................... .................. 13 5.1 c-bus clock ................................................................................................................. ......................... 13 6 performance specification ..................................................................................................... ...... 14 6.1 electrical performance ...................................................................................................... .................... 14 6.2 packaging................................................................................................................... ........................... 19 mx x com, inc. reserves the right to change specifications at any time and without notice.
digitally controlled analog i/o processor 3 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 1 block diagram 4:1 mux 1:4 mux a/d 10 bit a/din2 a/din3 a/din4 a/din1 high comparator a/d reg3 low comparator high comparator a/d reg4 low comparator high comparator a/d reg1 low comparator high comparator a/d reg2 low comparator dac1 8/10 bit dac3 8/10 bit dac2 8/10 bit dacout1 dacout2 dacout3 adc comp irq dv dd v bias av dd v ss 4-wire serial interface and logic control reply data command data clock oscillator and dividers xtal xtal/clock serial clock cs dv dd av dd mod2 in mod1 in 0 to 16db x 0.2db steps 0 to 12db x 0.4db steps mod1out mod2out mute2 mute1 figure 1: block diagram
digitally controlled analog i/o processor 4 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 2 signal list pin no. name type description 1 xtal output the output of the on-chip oscillator inverter. 2 xtal/clock input the input to the on-chip oscillator inverter, for external xtal circuit or clock. 3 serial clock input the 'c-bus' serial clock input. this clock, produced by the c, is used for transfer timing of commands and data to and from the device. see figure 5. 4 command data input the 'c-bus' serial data input from the c. data is loaded into this device in 8-bit bytes, msb (b7) first, and lsb (b0) last, synchronized to the serial clock. see figure 5. 5 reply data output the 'c-bus' serial data output to the c. the transmission of reply data bytes is synchronized to the serial clock under the control of the cs input. this tri-state output is held at high impedance when not sending data to the c. see figure 5. 6 cs input the 'c-bus' data loading control function. this input is provided by the c. data transfer sequences are initiated, completed or aborted by the cs signal. see figure 5. 7 irq output this output indicates an interrupt condition to the c by going to a logic '0'. this is a 'wire-orable' output, enabling the connection of up to 8 peripherals to 1 interrupt port on the c. this pin has a low impedance pulldown to logic '0' when active and a high-impedance when inactive. an external pullup resistor is required. the conditions that cause interrupts are indicated in the irq flag register and are effective if not disabled. 8 a/din1 input analog to digital converter input 1 (a/d1) 9 a/din2 input analog to digital converter input 2 (a/d2) 10 a/din3 input analog to digital converter input 3 (a/d3) 11 a/din4 input analog to digital converter input 4 (a/d4) 12 v ss power negative supply (ground) for both analog and digital supplies. 13 v bias output an analog bias line for the internal circuitry, held at av dd /2. this pin must be bypassed by a capacitor mounted close to the device pins. 14 n/c no internal connection. do not make any connection to this pin. 15 dacout1 output digital to analog converter no. 1 output (dac1) 16 dacout2 output digital to analog converter no. 2 output (dac2) 17 dacout3 output digital to analog converter no. 3 output (dac3) 18 n/c no internal connection. do not make any connection to this pin. 19 av dd power positive analog supply. analog levels and voltages are dependent upon this supply. this pin should be bypassed to v ss by a capacitor. 20 mod1 in input input to mod1 variable attenuator. 21 mod2 in input input to mod2 variable attenuator. 22 mod1 output output of mod1 variable attenuator. 23 mod2 output output of mod2 variable attenuator. 24 dv dd power positive digital supply. digital levels and voltages are dependent upon this supply. this pin should be bypassed to v ss by a capacitor.
digitally controlled analog i/o processor 5 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 3 external components dv dd av dd dv dd av dd v ss v bias mod1 out mod1 in mod2 out mod2 in irq xtal serial clock c-bus interface command data xtal/clock MX839 c3 r3 reply data cs 1 2 3 4 5 6 8 9 10 11 12 13 14 7 24 23 22 21 20 19 18 17 16 15 xtal dacout3 dacout2 dacout1 adcin1 adcin2 adcin3 adcin4 n/c n/c xtal/clock c2 c1 x1 r1 c6 dv dd r2 c4 c5 figure 2: recommended external components r1 1m : 5% c4 note 1 0.1f 20% r2 22k : 10% c5 0.1f 20% r3 note 1 10 : 10% c6 note 1 10.0f 20% c1 22pf 20% c2 22pf 20% c3 0.1f 20% x1 note 2, 3 100ppm table 1: recommended external components notes: 1. these values should be determined in regard to the amount of supply filtering required for d/a outputs. 2. if an external clock is to be used, then it should be connected to pin 2 and the components c1, c2, r1, and x1 omitted. the adc clock frequency is derived from the crystal or external clock by means of internal programmable dividers. see section 6 for details of crystal or external clock frequency range. 3. for best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of v dd , peak to peak. tuning fork crystals generally cannot meet this requirement. to obtain crystal oscillator design assistance, consult your crystal manufacturer.
digitally controlled analog i/o processor 6 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4 general description the device comprises four groups of related functions: variable attenuators, digital to analog converters, a multiplexed analog to digital converter with multiplexer, clock generator and four 8-bit magnitude comparators with variable reference levels. these functions are all controlled by the 'c-bus' serial interface and are described below: 4.1 variable attenuators the two variable attenuators have a range of 0 to -12db and 0 to -6db respectively and may be controlled independently. 4.2 digital to analog converters three dacs are provided with default resolutions of 8 bits, which are defined at the initial chip reset. in this mode the 'c-bus' data is transferred in a single byte. an option is provided to define any one or more of the dac resolutions to be 10 bits, then the dac requires the transfer of two 'c-bus' data bytes. the upper and lower dac reference voltages are defined internally as av dd and v ss respectively. the output voltage is expressed as: v out = av dd x (data / 2 n ) [volts] where, n is the dac resolution (8 or 10 bits) and data is the decimal value of the input code. for example: n = 8 and binary code = 11111111 therefore data = 255 v out = av dd x (255 / 256) [volts] any one of the three dac input latches might be loaded by sending an address/command byte followed by one or two data bytes to the 'c-bus' interface. the data is then latched and the static voltage is updated at the appropriate output. when a dac is disabled, its output is defined as open-circuit. 4.3 analog to digital converter and a/d clock generator a single successive approximation a/d is provided with four multiplexed inputs. after a general reset command $01, the a/d converter subsystem is disabled. to start conversions the clock control ($d0) and a/d control ($d7) registers must be written (refer to tables 2,6, and 8). please note that a/d channel 1 must be active for any other channel to work. also note that a/d control register bit 5 ( read ) should be set low prior to issuing a read a/d data x command to disable conversions so the data being read does not change during the read which could otherwise result in erroneous data being read. to re-enable conversions the a/d control register bit 5 ( read ) bit must be set back high. the internal a/d clock frequency (f a/d_clk ) is generated with a programmable clock generator. users have flexible control of this clock signal via the clock control register ($d0), divider set per table 6, and the choice of an external system clock signal or a dedicated crystal. f a/d_clk should be chosen not to exceed 1mhz. since the typical application is for monitoring slowly changing control voltages, a sample and hold circuit is not included at the input of the a/d. thus, for the analog to digital conversion to be accurate, the input signal should not change significantly during the conversion time. for n-bit accuracy (with a maximum error of 1lsb) the maximum signal linear rate of change, s, is defined by: ) 2 + n ( 1000 2 f av = s n a/d_clk dd [mv/ p s] where: n is the number of bits of accuracy with a maximum error of 1 lsb where: divider f = f xtal a/d_clk , divider is selected per table 6. for example: the most significant bits (n) of accuracy. for (n = 6) bit accuracy with av dd =5v and f a/d_clk = 1mhz s = 9.77 [mv/ p s] for (n = 8) bit accuracy with av dd =5v and f a/d _ clk = 1mhz s = 1.95 [mv/ p s] for (n = 10) bit accuracy with av dd =3.3v and f a/d_clk = 1mhz s = 0.27 [mv/ p s] the input signal should therefore be band limited to ensure the maximum signal linear rate of change is not exceeded for the desired accuracy.
digitally controlled analog i/o processor 7 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. after enabling conversions the user must allow time for all enabled channels to be digitized before reading the results via the c-bus. the minimum required time to wait is: a/d_clk conv_max f inputs' enabled of number ' ) 2 + 10 ( = t [seconds] upon disabling conversions the data for the most recent conversion completed for each channel will be available via the c-bus commands read a/d data x (addresses $dc, $dd, $de, $df) for input channels 1 through 4 respectively. do not forget to re-enable conversions by setting a/d control register bit 5, the read bit, back high after reading the desired a/d results. note that the magnitude comparators (see section 4.4) can be configured to monitor the a/d channel data in order to minimize the software burden of continuously reading the a/d channel data. it is not recommended to issue read a/d data x commands without first setting a/d control register bit 5, the read bit, low. an example c-bus transaction to do a conversion and read of a/d channel 1: hex address/ command write data byte 1 read data byte 1 read data byte 2 comment $01 n/a n/a n/a reset device $d0 $03 n/a n/a set f a/d_clk divider = 4 $d7 $70 n/a n/a enable conversion on a/d channel 1 $d7 $50 n/a n/a disable conversions after waiting t conv_max $dc n/a xxxxxxxx 000000xx read a/d channel 1 data $d7 $70 n/a n/a re-enable conversion on a/d channel 1 4.4 magnitude comparators and interrupt request high and low digital comparator reference levels are provided for the four digital magnitude comparators via the 'c-bus' interface. the digital input to the comparators is provided by the most significant 8 data bits of each a/d channel when the sampled data falls outside the high or low digital comparator reference levels the status register is updated and the irq pin is pulled low. when a reference level is set to '0', its irq is disabled. 4.5 software description 4.5.1 address/commands instructions and data are transferred via the 'c-bus' in accordance with the timing information provided in figure 5. instruction and data transactions to and from the fx839 consist of an address/command byte followed by either: (i) a control or dac data write (1 or 2 bytes) or, (ii) a status or a/d data read (1 or 2 bytes)
digitally controlled analog i/o processor 8 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4.5.2 write only register (8-bit and 16-bit) hex address/ comman d register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) $01 reset n/a n/a n/a n/a n/a n/a n/a n/a clock divider $d0 control 0 0 0 0 0 bit 2 bit 1 bit 0 variable mod1 mod1 $d2 attenuator (1) 0 0 enable bit 4 bit 3 bit 2 bit 1 bit 0 variable mod2 mod2 attenuator (2) 0 0 enable bit 4 bit 3 bit 2 bit 1 bit 0 dac nbit nbit nbit dac1 dac2 dac3 $d3 control dac1 dac2 dac3 0 enable enable enable 0 dac1 data $d4 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 *see note 1 (2) 0 0 0 0 0 0 bit 9 bit 8 dac2 data $d5 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 *see note 1 (2) 0 0 0 0 0 0 bit 9 bit 8 dac3 data $d6 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 *see note 1 (2) 0 0 0 0 0 0 bit 9 bit 8 a/d a/din1 a/din2 a/din3 a/din4 $d7 control 0 1 read active active active active 0 mag comp one magnitude comparator upper level $d8 levels (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp one magnitude comparator lower level levels (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp two magnitude comparator upper level $d9 levels (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp two magnitude comparator lower level levels (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp three magnitude comparator upper level $da levels (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp three magnitude comparator lower level levels (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp four magnitude comparator upper level $db levels (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mag comp four magnitude comparator lower level levels (2) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 table 2: write only register (8-bit and 16-bit) note 1. a second byte is expected by the 'c-bus' interface only when the 'nbit dac n ' bit of the 'dac control register' is set high. otherwise, the data transfer is a single byte (bit 7 to bit 0).
digitally controlled analog i/o processor 9 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4.6 read only registers (8-bit and 16-bit) hex address/ command register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) $d1 irq flags hirqf 4 lirqf 4 hirqf 3 lirqf 3 hirqf 2 lirqf 2 hirqf 1 lirqf 1 $dc a/d data1 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (2) 0 0 0 0 0 0 bit 9 bit 8 $dd a/d data2 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (2) 0 0 0 0 0 0 bit 9 bit 8 $de a/d data3 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (2) 0 0 0 0 0 0 bit 9 bit 8 $df a/d data4 (1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (2) 0 0 0 0 0 0 bit 9 bit 8 table 3: read only registers (8-bit and 16-bit) 4.7 write only register description 4.7.1 reset register (hex address $01) the reset command has no data attached to it. it sets the device registers into the specific states listed below: register name bit 7 (d7) bit 6 (d6) bit 5 (d5) bit 4 (d4) bit 3 (d3) bit 2 (d2) bit 1 (d1) bit 0 (d0) clock control 0 0 0 0 0 0 0 0 dac control 0 0 0 0 0 0 0 0 dac1 data 1 00000000 dac2 data 1 00000000 dac3 data 1 00000000 a/d control 0 0 0 0 0 0 0 0 variable attenuator (1) 0 0 0 0 0 0 0 0 (2)00000000 mag comp one levels (1) 0 0 0 0 0 0 0 0 (2)00000000 mag comp two levels (1) 0 0 0 0 0 0 0 0 (2)00000000 mag comp three levels (1) 0 0 0 0 0 0 0 0 (2)00000000 mag comp four levels (1) 0 0 0 0 0 0 0 0 (2)00000000 table 4: reset register (hex address $01) note 1. default resolution is defined as 8-bits.
digitally controlled analog i/o processor 10 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4.7.2 clock control register (hex address $d0) this register controls the a/d clock divide ratio: bits 7 to 3 reserved for future use. these bits should be set to '0'. divider (bit 2 - bit 0) the xtal input clock divide ratio, which sets the a/d sample clock frequency, is defined in the following table. table 5: clock control register (hex address $d0) bit 2 bit 1 bit 0 function 000powersave 001 y 1 010 y 2 011 y 4 100 y 8 101 y 16 110 y 32 111 y 64 table 6: divider (bit 2 - bit 0)
digitally controlled analog i/o processor 11 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4.7.3 variable attenuator register (hex address $d2) this is a 16-bit register. byte (1) is sent first. bits 0 - 5 of the first byte in this register are used to enable and set t he attenuation of the modulator 1 amplifier. bits 0 - 5 of the second byte in this register are used to enable and set the attenuation of the modulator 2 amplifier. see table 7. 5 4 3 2 1 0 mod. 1 attenuation 5 4 3 2 1 0 mod. 2 attenuation 0 x x x x x disabled (v bias ) 0 x x x x x disabled (v bias ) 1 0 0 0 0 0 >40db 1 0 0 0 0 0 >40db 100001 12.0db 100001 6.0db 100010 11.6db 100010 5.8db 100011 11.2db 100011 5.6db 100100 10.8db 100100 5.4db 100101 10.4db 100101 5.2db 100110 10.0db 100110 5.0db 100111 9.6db 100111 4.8db 101000 9.2db 101000 4.6db 101001 8.8db 101001 4.4db 101010 8.4db 101010 4.2db 101011 8.0db 101011 4.0db 101100 7.6db 101100 3.8db 101101 7.2db 101101 3.6db 101110 6.8db 101110 3.4db 101111 6.4db 101111 3.2db 110000 6.0db 110000 3.0db 110001 5.6db 110001 2.8db 110010 5.2db 110010 2.6db 110011 4.8db 110011 2.4db 110100 4.4db 110100 2.2db 110101 4.0db 110101 2.0db 110110 3.6db 110110 1.8db 110111 3.2db 110111 1.6db 111000 2.8db 111000 1.4db 111001 2.4db 111001 1.2db 111010 2.0db 111010 1.0db 111011 1.6db 111011 0.8db 111100 1.2db 111100 0.6db 111101 0.8db 111101 0.4db 111110 0.4db 111110 0.2db 111111 0db 111111 0db x = don't care mod1 enable (bit 5, first byte) when this bit is '1' the mod1 attenuator is enabled. when this bit is '0' the mod1 attenuator is disabled (i.e. powersaved). mod2 enable (bit 5, second byte) when this bit is '1' the mod2 attenuator is enabled. when this bit is '0' the mod2 attenuator is disabled (i.e. powersaved). (bits 7 and 6, first and second bytes) reserved for future use. these should be set to '0'. table 7: variable attenuator register (hex address $d2)
digitally controlled analog i/o processor 12 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4.7.4 dac control register (hex address $d3) this register controls the resolution and the number of enabled dac outputs: nbit dac1 (bit 7) nbit dac2 (bit 6) nbit dac3 (bit 5) these bits define the input resolutions for each of the four dacs. when 'nbit dac n ' is '0' the resolution of dac n is 8-bits. when 'nbit dac n is '1' the resolution of dac n is 10-bits. (bit 4) reserved for future use. this bit should be set to '0'. dac1 enable (bit 3) dac2 enable (bit 2) dac3 enable (bit 1) these bits allow any one or more of the three dacs to be powered up. when '0' the dac n is powered down and the output is high impedance. when '1' the dac is powered on and the output voltage is defined by the dac data registers. (bit 0) reserved for future use. this bit should be set to '0'. 4.7.5 dac1 data register (hex address $d4) 4.7.6 dac2 data register (hex address $d5) 4.7.7 dac3 data register (hex address $d6) the data in these three registers sets the analog voltage at the output of dac1, dac2 and dac3. this data will consist of one or two bytes depending on the defined input resolution that is set by bits 7, 6 and 5 of the dac control register. when operating with 10-bit resolution bit 7 to bit 2 of the dac n data register second data byte must be set to "0". 4.7.8 a/d control register (hex address $d7) this register sets which channels are active and enables conversion mode or read mode. (bit 7) reserved for future use. this bit should be set to '0'. (bit 6) reserved for future use. this bit should be set to 1. read (bit 5) when this bit is set to 1 all active channels are continuously sampled and the latest converted data stored for each channel. when this bit is set to 0 all conversions are stopped so that they may be read. a/d1 active (bit 4) a/d2 active (bit 3) a/d3 active (bit 2) a/d4 active (bit 1) these bits allow any one or more of the four a/d input channels to be enabled. when '0' the a/din n input voltage is not converted. when '1' the a/din n input is defined as active and the input voltage is converted. a/d1 must be active for any other channel to be active. (bit 0) reserved for future use. this bit should be set to 0. table 8: a/d control register (hex address $d7) 4.7.9 mag comp one levels (hex address $d8) 4.7.10 mag comp two levels (hex address $d9) 4.7.11 mag comp three levels (hex address $da) 4.7.12 mag comp four levels (hex address $db) each address controls the relevant numbered a/d magnitude comparator. the first byte, transmitted with the most significant bit first, sets the magnitude comparator upper reference level and the second byte sets the magnitude comparator lower reference level. when a reference level's value is set to '0' its irq is disabled. in general, if a reference levels value is r (unsigned decimal value of data byte) [] volts 256 r av = v dd ref
digitally controlled analog i/o processor 13 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 4.8 read only register description 4.8.1 irq flags register (hex address $d1) hirqf1 (bit 1) hirqf2 (bit 3) hirqf3 (bit 5) hirqf4 (bit 7) these bits are set if the relevant digital magnitude comparator input exceeds its upper reference level. these bits are reset to '0' immediately after reading the irq flags register. when any of these bits are set, an interrupt will be generated if the relevant reference level is not zero. lirqf1 (bit 0) lirqf2 (bit 2) lirqf3 (bit 4) lirqf4 (bit 6) these bits are set if the relevant digital magnitude comparator input falls below its lower reference level. these bits are reset to '0' immediately after reading the irq flags register. when any of these bits are set, an interrupt will be generated if the relevant reference level is not zero. table 9: irq flags register (hex address $d1) 4.8.2 a/d data1 register (hex address $dc) 4.8.3 a/d data2 register (hex address $dd) 4.8.4 a/d data3 register (hex address $de) 4.8.5 a/d data4 register (hex address $df) this data will consist of two bytes each. bit 7 to bit 2 of the second data byte will be set to '0'. bits 0-7 of the first by te are the lease significant 8 bits while bits 0-1 of the second byte are the most significant 2 bits of the 10 bit conversion. the analog input (v in ) is converted to a 10-bit digital word (w) according to: 1024 av v = w dd in the bits of word (w) are returned in 2 bytes as follows: 7654321 0 return byte 1 w 7 w 6 w 5 w 4 w 3 w 2 w 1 w 0 return byte 2 000000w 9 w 8 5 application 5.1 c-bus clock although this is specified as a 500khz clock for compatibility with other c-bus devices, the MX839 c-bus will operate over a much wider range. users should ensure that the c-bus clock is at least 4 times slower than the crystal or external clock on pin 2 of the MX839.
digitally controlled analog i/o processor 14 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 6 performance specification 6.1 electrical performance 6.1.1 absolute maximum ratings exceeding these maximum ratings can result in damage to the device. general notes min. max. units supply (v dd - v ss ) (either av dd or dv dd ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current av dd -30 30 ma dv dd -30 30 ma v ss -30 30 ma any other pin -20 20 ma av dd - dv dd note 1, 2 -100 100 mv dw / p package total allowable power dissipation at t amb = 25c 800 mw derating above 25c 13 mw/c above 25c storage temperature -55 125 c operating temperature -40 85 c ds package total allowable power dissipation at t amb = 25c 550 mw derating above 25c 9 mw/c above 25c storage temperature -55 125 c operating temperature -40 85 c note: 1. it is recommended that av dd be connected to dv dd through a filter. 2. it is also recommended that av dd and dv dd voltages be tightly ac coupled to v ss with a capacitor. 6.1.2 operating limits correct operation of the device outside these limits is not implied. min. max. units supply (v dd - v ss ) (either av dd or dv dd )3.05.5v operating temperature -40 85 c xtal frequency 0.5 6.0 mhz
digitally controlled analog i/o processor 15 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 6.1.3 operating characteristics for the following conditions unless otherwise specified: av dd = dv dd = v dd = 3.3v to 5.0v, t amb = 25c notes min. typ. max. units dc parameters supply voltage 3.0 5.0 5.5 v supply difference (av dd - dv dd ) -100 100 mv i dd v dd = 5v powersaved 250 400 p a not powersaved 4.5 7.0 ma v dd = 3.3v powersaved 150 250 p a not powersaved 2.5 4.0 ma 'c-bus' interface input logic '1' 70% dv dd input logic '0' 30% dv dd input leakage current (logic '1' and '0') -1.0 1.0 a input capacitance 7.5 pf output logic '1' (i oh = 120a) 90% dv dd output logic '0' (i ol = 360a) 10% dv dd dacs and output buffers (guaranteed monotonic) un-loaded performance resolution 8 or 10 bits internal dac settling time (to 0.5 lsb) 10.0 s integral non-linearity figure 4 7 8 bit mode 3.0 lsbs 10 bit mode 5.0 lsbs differential non-linearity figure 3 6 8 bit mode 1.0 lsbs 10 bit mode 1.0 lsbs buffer slew rate (with 20pf load) tbd v/s buffer output resistance 200 : zero error (for 0000 hex code input) -20 0 20 mv rms output noise voltage 1 10 v loaded performance 2 output voltage with 5k : resistive load to ground digital code = 3ff hex 34.79 v digital code = 200 hex , 10 bit 3 2.495 v digital code = 80 hex , 8 bit 3 2.495 v output voltage with 5k : resistive load to v dd digital code = 000 hex 3 200 mv minimum resistive load 4 1.0 k :
digitally controlled analog i/o processor 16 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. notes min. typ. max. units a/ds and multiplexed inputs (guaranteed monotonic) resolution 10 bits input signal 'linear rate of change' v dd = 3.3v, and f a/d_clk = 1mhz for 1 bit error 0.27 mv/s conversion time f a/d_clk = 1mhz 12 s integral non-linearity figure 4 7 2.0 lsbs differential non-linearity figure 3 6 1.0 zero error -20 20 mv a/d clock frequency (f a/d_clk ) 1.0 tbd mhz input capacitance tbd pf variable attenuators nominal adjustment range mod1 attenuator 0 12.0 db mod2 attenuator 0 6.0 db attenuation accuracy -1.0 1.0 db step size mod1 0.2 0.4 0.6 db mod2 0.1 0.2 0.3 db output impedance 5 600 : bandwidth (-3db) 100 khz input impedance 15 k : magnitude comparators and interrupt request resolution 8 bits output logic '0' at irq (i ol = 360a and pull-up resistor r2 = 22k : 10% to dv dd ) 10% dv dd 'off' state leakage current at irq v out = dv dd 10 a xtal/clock input frequency range 8 0.5 6.0 mhz 'high' pulse width 40 ns 'low' pulse width 40 ns input impedance (at 100hz) 10 m : gain (input = 1mv rms at 100hz) 20 db
digitally controlled analog i/o processor 17 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. operating characteristics notes: 1. measured over a 0 to 30khz band. 2. the extremes of the dac output range (when resistively loaded) is affected by the output impedance of the dac buffer. under these conditions, the output impedance can approach 200 : . however; when the output is operating well within the supply; the output impedance will be significantly lower, thereby improving the loaded performance. 3. r load = 5k : av dd = 5.0v. 4. loads less than 1k : will produce output distortion. 5. small signal impedance, at av dd = 5v and t amb = 25c. 6. differential non-linearity is defined as the difference in width between adjacent code midpoints and the width of an ideal lsb, divided by the width of an ideal lsb. see figure 3. 7. integral non-linearity is defined as the width difference between an actual code midpoint and the line of best fit through all code midpoints, divided by the width of an ideal lsb. see figure 4. 8. 6mhz operation at v dd = 5.0v only. the c-bus clock must be at lest 4 times slower than the xtal/clock frequency. analog output digital input ideal response actual response code width=2lsbs differential non-linearity=1lsb 0v 000$ to $2ff to av dd figure 3: differential non-linearity of a d/a converter 000 040 080 0c0 analog output 100 140 180 1c0 200 240 280 2ff 0/768 64/768 128/768 192/768 256/768 320/768 384/768 448/768 512/768 576/768 640/768 704/768 768/768 digital input 5 lsbs ideal response actual response figure 4: integral non-linearity of a d/a converter
digitally controlled analog i/o processor 18 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 6.1.4 timing for the following conditions unless otherwise specified: dv dd = 3.3v to 5.0v, t amb = 25c parameter min. typ. max. units t cse "cs-enable to clock-high" 2.0 s t csh last "clock-high to cs-high" 4.0 s t hiz "cs-high to reply output 3-state" 2.0 s t csoff "cs-high" time between transactions 2.0 s t nxt "inter-byte" time 4.0 s t ck "clock-cycle" time 2.0 s 7 7 7 7 7 3 3 3 3 3 5 5 5 5 5 1 1 1 1 1 6 6 6 6 6 2 2 2 2 2 4 4 4 4 4 0 0 0 0 0 serial clock msb msb lsb lsb command data reply data address/command byte first data byte last data byte last reply data byte first reply data byte logic level is not important cs t cse t ck t nxt t csh t nxt t csoff t hiz figure 5: 'c-bus' timing timing notes: 1. depending on the command, 1 or 2 bytes of command data are transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. reply data is read from the peripheral msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into and out of the peripheral on the rising serial clock edge. 3. loaded commands are acted upon at the end of each command. 4. to allow for differing c serial interface formats 'c-bus' compatible ics are able to work with either polarity serial clock pulses.
digitally controlled analog i/o processor 19 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. 6.2 packaging 0.597 (15.16) package tolerances a b c e h typ. max. min. dim. j p x w t y k l 0.105 (2.67) 0.093 (2.36) 0.419 (10.64) 45 7 0 10 0.050 (1.27) 0.046 (1.17) 0.613 (15.57) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.390 (9.90) 0.020 (0.51) 0.003 (0.08) 0.009 (0.23) 0.0125 (0.32) 0.013 (0.33) 0.020 (0.51) 0.036 (0.91) 0.286 (7.26) z note : all dimensions in inches (mm.) angles are in degrees 5 5 pin 1 a b x p j y c h k e l t w z alternative pin location marking figure 6: 24-pin soic mechanical outline: order as part no. MX839dw note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e h typ. max. min. dim. j p x t y z l 0.079 (2.00) 0.066 (1.67) 0.312 (7.90) 0 7 4 8 9 10 0.037 (0.95) 0.328 (8.33) 0.213 (5.39) 0.026 (0.65) 0.022 (0.55) 0.301 (7.65) 0.008 (0.21) 0.002 (0.05) 0.005 (0.13) 0.009 (0.22) 0.010 (0.25) 0.015 (0.38) 0.318 (8.07) 0.205 (5.20) x c h p j y e z l t pin 1 a b figure 7: 24-pin ssop mechanical outline: order as part no. MX839ds
digitally controlled analog i/o processor 20 MX839 preliminary information ? 1998 mx x com inc. www. mxcom.com tele: 800 638-5577 336 744-5050 fax: 336 744-5054 doc. # 20480164.002 4800 bethania station road, winston-salem, nc 27105-1201 usa all trademarks and service marks are held by their respective co mpanies. note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e e1 h typ. max. min. dim. j j1 p y t k l 0.220 (5.59) 0.555 (14.04) 0.670 (17.02) 7 0.160 (4.05) 1.270 (32.26) 0.151 (3.84) 0.100 (2.54) 0.121 (3.07) 0.600 (15.24) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.008 (0.20) 0.015 (0.38) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 1.200 (30.48) 0.500 (12.70) h k l j1 j1 j j p p c c b b a a pin1 pin1 t t e e e1 e1 y figure 8: 24-pin pdip mechanical outline: order as part no. MX839p

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